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| to learn more about on semiconductor, please visit our website at www.onsemi.com please note: as part of the fairchild semiconductor integration, some of the fairchild orderable part numbers will need to change in order to meet on semiconductors system requirements. since the on semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the fairchild part numbers will be changed to a dash (-). this document may contain device numbers with an underscore (_). please check the on semiconductor website to verify the updated device numbers. the most current and up-to-date ordering information can be found at www.onsemi.com . please email any questions regarding the system integration to fairchild_questions@onsemi.com . is now part of on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of on semiconductors product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or circuit, and specifcally disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. typical parameters which may be provided in on semiconductor data sheets and/or specifcations can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classifcation in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its offcers, employees, subsidiaries, affliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affrmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
? semiconductor components industries, llc, 201 6 1 publication order number: december 2016 - rev. 1.0 fan6291qf / d f an6291qf /fan6291qh compact secondary - side adaptive charging controller synchronous rectifier control and usb type - c control fan 6291q f/fan6291qh are highly integrated, secondary - side power adaptor controller s compatible with the quick charge 3 .0 (qc3.0) protocol. i nternally adopt ed synchronous rectifier control helps for less bom counts as well as for easy design . fan 6291qf /fan6291qh are also a source only usb type - c controller s which are optimized for mobile charger s and power adapter s . i t supports standard 3 a vbus current level. n - channel mosfet is compatible as a l oad switch , and helps to reduce bom cost . the internal two operational amplifiers control adaptive constant outp ut voltage and adaptive constant output current. the o utputs of the two amplifiers are tied together in open - drain configuration. fan 6291qf /fan6291qh enables adaptor output voltage and current adjustment when quick charge 3.0 protocol is acknowledged. according to request from a battery charger of a portable device , output voltage is adjusted up to 12 v . when a p ortable d evice that implements non - compliant protocols is attached , it just maintains the default output, ( 5 v ) for safety of the p ortable d evi ce . fan 6291 qf/fan6291qh incorporates adaptive output over - voltage and under - voltage protections to improve system reliability . features ? compatible with q uick c harge 3 .0 (qc3.0) protocol ? auto - detection supporting 2.4 a apple products ? type - c control for standard 3 a vbus current ? n - channel mosfet control as a type - c load switch ? internal synchronous rectifier control circuit ? secondary - side constant voltage (cv) and constant current (cc) regulation with two operational amplifiers ? small current sensing resist or (30 m ) for h igh e fficiency ? protections for safe operation ; output over - voltage - protection , output under - voltage - protection for qc2.0 , data line (d+/d - ) over - voltage - protection ? built - in output capacitor bleeding function for fast discharging during change of output mode ? built - in cable - drop compensation typical applications ? battery chargers for smart phones, feature phones, and tablet pcs ? ac - dc adapters for portable devices that require cv/cc control www. onsemi.com 1 14 1 14 tssop - 14 marking diagram 1 st line: f: corporate logo z: assembly plant code x: year code y: week code tt : die run code 2 nd line: 6291q: ic part n ame x: series line - up name 3 rd line: mtcf pin connections (top view) ordering information see detailed ordering and shipping information in the package dimensions section on page 19 of this data sheet. z x y t t 6 2 9 1 q x m t c f d p d n v r e f i r e f c s l p c g n d g a t e 1 1 1 4 3 2 1 3 1 2 1 4 s f b v i n 1 0 5 c c 1 l g a t e 9 6 c c 2 b l d 8 7 fan6291qf /fan6291qh www. onsemi.com 2 figure 1 fan6291q f and fan629 1 qh typical application schematic figure 2 . fan6291q f and fan6291qh function block diagram s r m o s f e t l m r h v r s n u r s e n s e f u s e t h c i n 1 c s n u c o u t b d l c i n 2 d s n u a c i n l m t r a n s f o r m e r u s b t y p e - c b l d l g a t e v i n v r e f g a t e l p c d p d n g n d c s d n d p g n d t x 1 + t x 1 - v b u s c c 1 d + d - s b u 1 v b u s r x 2 - r x 2 + g n d i r e f c c 1 c c 1 s f b c c 2 c c 2 l o a d s w i t c h d n d p c c 1 c c 2 g n d t x 2 + t x 2 - v b u s c c 2 d + d - s b u 2 v b u s r x 1 - r x 1 + g n d d n d p v b u s v b u s v b u s v b u s v b u s q 1 r v s h r v s l r c s c v d d c v s q 1 r g a t e r f d v d d f a n 6 2 9 1 f a n 6 0 2 g a t e c s v d d v s h v n c f b g n d 4 3 1 2 1 0 5 6 9 f m a x i m i n 8 7 v d d - o n / v d d - o f f i n t e r n a l b i a s ( v d d ) x a v c c r c a b l e d r o p c o m p e n s a t i o n m o d e m o d e m o d e c h a n g e v c v r v c c r v d d i r e f c s g n d v r e f v i n s f b o v p p r o t e c t i o n m o d e o v p l p c s r q g a t e g a t e d r i v e r p w m b l o c k v l p c - e n g r e e n m o d e l i n e d e t e c t i o n f u n c t i o n v l p c - t h c a l c u l a t e v l p c - e n r e s e t p r o t o c o l c o m m u n i c a t i o n ( a u t o - d e t e c t i o n ) m o d e m o d e c h a n g e c a b l e f a u l t d n d p d a t e l i n e o v p v d d v i n u v p p r o t e c t i o n m o d e u v p c a b l e f a u l t l g a t e t y p e - c d e t e c t i o n c c 2 c c 1 b l d c a b l e f a u l t s r o f f - t i m e d e c i s i o n m o d e c h a n g e t y p e - c d e t a c h c a b l e f a u l t fan6291qf /fan6291qh www. onsemi.com 3 pin function description series line - up table pin no. pin name description 1 dp communication interface positive terminal. this pin is tied to the usb d+ data line input. 2 dn communication interface negative terminal. this pin is tied to the usb d - data line input. 3 vref output voltage sensing terminal . non - inverting terminal of the internal cv loop amplifier. this pin is used for constant voltage regulation . 4 iref constant current amplifying signal. the voltage on this pin represents the amplified current sense signal , also used for constant current regulation . it is tied to the internal cc loop amplifier's non - inverting terminal. 5 sfb secondary feedback. common output of the open - drain operation amplifiers. typically an opto - coupler is connected to this pin to provide feedback signal to the primar y - side pwm controller. 6 cc1 configuration channel 1. this pin is used to detect connections of type - c cables and connectors. it is tied to the usb type - c cc1. 7 cc2 configuration channel 2. this pin is used to detect connections of type - c cables and connectors. it is tied to the usb type - c cc2. 8 bld bleeder. this pin is tied to the vbus pin of type - c connector to discharge an output capacitor. 9 lgate load switch gate. this pin is tied to the gate of the load switch 10 vin input voltage. this pin is tied to the output of the adaptor not only to monitor output voltage but also to supply internal bias. ic operating current, and mosfet gate - drive current are supplied through this pin. 11 gate gate drive output. totem - pole output to drive an external sr mosfet. 12 gnd ground. 13 lpc sr mosfet drain voltage detection. this pin detect s the voltage on the secondary winding for synchronous rectifier control . 14 cs current sensing amplifier negative terminal. output current is sensed through this terminal for green mode control, cable drop compensation, and constant current control . name output voltage and its n ominal o utput c urrent uvp o peration v o = 3.6 ~ 6 v v o = 6 .2 ~ 9 v v o = 9 .2 ~ 12 v fan6291qf 3.0 a 2.0 a 1.5 a pull - down sfb fan6291qh 3.0 a 3.0 a 2.0 a reduce cc fan6291qf /fan6291qh www. onsemi.com 4 maximum ratings ( note 1 , 2 , 3 ) 1. stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, devi ce functionality should not be assumed, damage may occur and reliability may be affected. 2. all voltage values, except differential voltages, are given with respect to the gnd pin. 3. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 4. meets jedec standards js - 001 - 2012 and jesd 22 - c101. thermal characteristics ( note 5 ) 5. t a =25c unless otherwise specified. recommended operating ranges ( note 6 ) 6. functional operation a bove the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. rating symbol value unit vin pin input voltage v in 2 0 v sfb pin input voltage v sfb 20 v bld pin input voltage v bld 2 0 v lgate pin input voltage v lgate 2 0 v cc1 pin input voltage v cc1 - 0.3 to 6 v cc2 pin input voltage v cc2 - 0.3 to 6 v iref pin input voltage v iref - 0.3 to 6 v vref pin input voltage v vref - 0.3 to 6 v cs pin input voltage v cs - 0.3 to 6 v dp pin input voltage v dp - 0.3 to 14 v dn pin input voltage v dn - 0.3 to 14 v lpc p in input voltage v lpc - 0.3 to 6.5 v gate pin input voltage v gate - 0.3 to 6 v power dissipation (t a =25 ? c) p d 0.62 w operating junction temperature t j - 40 to 150 ? c storage temperature range t stg - 40 to 150 ? c lead temperature, ( s oldering, 10 seconds) t l 260 ? c human body model, ansi/esda/jedec js - 001 - 2012 ( note 4 ) esd hbm 3 kv charged device model, jesd22 - c101 ( note 4 ) esd cdm 1.75 kv rating symbol value unit thermal characteristics, thermal resistance, junction - to - air thermal reference, junction - to - top r ja r j t 162 16.5 c/w rating symbol min max unit vin pin input voltage v in 0 16 v sfb pin input voltage v sfb 0 16 v bld pin input voltage v bld 0 16 v lgate pin input voltage v lgate 0 19.5 v cc1 pin input voltage v cc1 0 5.8 v cc2 pin input voltage v cc2 0 5.8 v iref pin input voltage v iref 0 1 v vref pin input voltage v vref 0 3.5 v cs pin input voltage v cs - 0.1 0 v dp pin input voltage v dp 0 6 v dn pin input voltage v dn 0 6 v lpc pin input voltage v lpc 0 5 v gate pin input voltage v gate 0 5.5 v fan6291qf /fan6291qh www. onsemi.com 5 electrical characteristics v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit vin section continuous operating voltage ( 7 ) v in - op 16 v operating supply current v in =5 v, v cs = - 6 0 mv i in - op - 5v 8 ma operating supply current v in = 12 v, v cs = - 6 0 mv i in - op - 12v 8 ma 5 v green mode operating supply current v in =5 v, v cs =0 m v i in - green 1.2 1.6 ma vin - uvp section voltage difference between gnd and cs for fixed uvp current ( i o - uvp.typ = 217 m a ) only for fan6291qh v cs - uvp 3.0 6.5 10.0 mv v in under - voltage - protection enable, 9 v for qc2.0 9 v m ode v in - uvp - l - 9v 5.00 5.50 6.00 v v in under - voltage - protection enable, 12 v for qc2.0 12 v m ode v in - uvp - l - 12 v 7.50 8.00 8.50 v v in under - voltage - protection dis able, 9 v for qc2.0 9 v m ode v in - uvp - h - 9v 5.50 6.00 6.50 v v in under - voltage - protection dis able, 12 v for qc2.0 12 v m ode v in - uvp - h - 12 v 8.00 8.50 9.00 v cc mode uvp debounce time t d - vin - uvp 45 60 75 ms vin - ovp section output over - voltage protection through v in pin at v o =3.6 ~ 5 v v in - ovp - 5v 5. 5 6.0 6. 5 v output over - voltage protection through v in pin at v o =5.2 ~ 6 v v in - ovp - 6 v 8.1 8.4 8.7 v output over - voltage protection through v in pin at v o =6.2 ~ 9 v v in - ovp - 9v 10. 3 10.8 11. 3 v output over - voltage protection through v in pin at v o =9.2 ~ 12 v v in - ovp - 12 v 1 3.6 14.4 1 5.0 v ovp debounce time t d - ovp 22 33 44 s internal bias section turn - on threshold voltage v in increases v in - on 2.9 3.2 3.4 v turn - o ff threshold voltage v in decreases after v in = v in - on v in - o ff 2.8 2.9 3.0 v hysteresis of turn - off threshold voltage v in decreases after v in = v in - on v in - off - hys 0. 3 v turn - on debounce time t v in - on - debounce 50 s turn - off debounce time t v in - off - debounce 200 s output voltage releasing latch mode ( 8 ) v latch - off 1.5 2.0 2.5 v constant current sensing section current - sense amplifier gain ( 7 ) v in =5 v, v cs = - 6 0 mv a v - ccr 10 v/v voltage difference between gnd and cs at i o - nominal =3.0 a of fan6291qf ( 8 ) i o = 3.0 ~ 3. 4 a, i otyp = 3. 2 a (3 mv o ffset) v cs - 3.0a - qf 90.0 93.0 96.0 mv voltage difference between gnd and cs at i o - nominal =2.0 a of fan6291qf ( 8 ) i o = 2.0 ~ 2.3 a, i otyp = 2. 15 a (3 mv o ffset) v cs - 2.0a - qf 59.5 62.0 64.5 m v voltage difference between gnd and cs at i o - nominal =1.5 a of fan6291qf ( 8 ) i o = 1.5 ~ 1. 8 a, i otyp = 1.6 5 a (3 mv o ffset) v cs - 1.5a - qf 43.5 46.0 48.5 m v voltage difference between gnd and cs at i o - nominal =3.0 a of fan6291qh ( 8 ) i o = 3.0 ~ 3. 4 a, i otyp = 3. 2 a (3 mv o ffset) v cs - 3.0a - qh 90.0 93.0 96.0 mv voltage difference between gnd and cs at i o - nominal =2.0 a of fan6291qh ( 8 ) i o = 2.0 ~ 2. 4 a, i otyp = 2. 2 a (3 mv o ffset) v cs - 2.0a - qh 62.5 65.0 67.5 m v current - sensing input impedance ( 8 ) z cs 4 m? voltage difference between gnd and cs for green mode r cs = 3 0 m ? v cs - green 2 5 8 mv fan6291qf /fan6291qh www. onsemi.com 6 electrical characteristics (continued) v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit constant current sensing section (continued) voltage difference between gnd and cs for green mode only for under 4.8 v mode of qc3.0, r cs = 3 0 m ? v cs - green - lowqc3.0 34 39 44 mv green mode enable debounce time after v cs fan6291qf /fan6291qh www. onsemi.com 7 electrical characteristics (continued) v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit protocol section_quick charge 2.0 interface dp low threshold voltage v dpl 0.2 4 0.25 0.2 8 v dp high threshold voltage v dph 1.95 2.05 2.15 v dn low threshold voltage v dnl 0.30 0.35 0.40 v dn high threshold voltage v dnh 1.95 2.05 2.15 v dp and dn high debounce time t bc1.2 1.0 1.2 1.4 s dp disconnect debounce time t disconnect 5 10 15 ms dn low debounce time, vdn < vdnl t toggle 1.0 ms mode - change debounce time t v_change 20 40 60 ms blanking time after mode change t v_request 60 100 ms dp pull low resistance r dp 300 1120 1500 k dn pull low resistance r dn 14.25 19.53 24.80 k protocol section_quick charge 3.0 interface mode - change debounce time v dp =0.6, v dn =3.3 v t v_change 20 40 60 ms mode - change debounce time for continuous mode for t active and t inactive t cont_change 100 150 200 s vin voltage range for continuous mode ( 7 ) v in_cont_ range 3.6 12 v table 1. quick c harge 3.0 & 2.0 output modes mode v dp (typ.) v d n (typ.) v ou t mode 1 0.6 v 0 v 5 v mode 2 3.3 v 0.6 v 9 v mode 3 0.6 v 0.6 v 12 v mode 4 0.6 v 3.3 v continuous mode mode 5 3.3 v 3.3 v reserved fan6291qf /fan6291qh www. onsemi.com 8 electrical characteristics (continued) v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit type - c section source current on cc1 pin v in =5 v, v cc2 =0 v i p - cc1 304 330 356 a source current on cc2 pin v in =5 v, v cc1 =0 v i p - cc2 304 330 356 a input impedance on cc1 pin z open - cc1 126 k input impedance on cc2 pin z open - cc1 126 k ra impedance detection threshold on cc1 pin v in =5 v, v cc2 =0 v, decreasing v cc1 v ra - cc1 0.75 0.80 0.85 v ra impedance detection threshold on cc2 pin v in =5 v, v cc1 =0 v, decreasing v cc2 v ra - cc2 0.75 0.80 0.85 v rd impedance detection threshold on cc1 pin v in =5 v, v cc2 =0 v, increasing v cc1 v rd - cc1 2.45 2.60 2.75 v rd impedance detection threshold on cc2 pin v in =5 v, v cc1 =0 v, increasing v cc2 v rd - cc2 2.45 2.60 2.75 v ufp attachment debounce time v in =5 v, v cc2 =0 v, increasing v cc1 t cc - attach - debounce 150 200 250 ms ufp detachment debounce time v in =5 v, v cc2 =0 v, decreasing v cc1 t cc - detach - debounce 10 15 20 m s gate high voltage at 5.5 v v in =5.5 v v ngate - 5.5v 9.0 v gate high voltage at 9 v v in =9 v v ngate - 9v 12.5 v gate high voltage at 12 v v in =12 v v ngate - 12v 15.5 v protocol section_auto detection default dp voltage when f loating 2.75 v s upply m ode v dp_2.75v 2.65 2.75 2.85 v default d n voltage when f loating 2.75 v s upply m ode v dn_2.75v 2.65 2.75 2.85 v dp p in o utput i mpedance in d efault m ode 2.75 v s upply m ode r dp_2.75v 23 28 33 k dn p in o utput i mpedance in d efault m ode 2.75 v s upply m ode r dn_2.75v 23 28 33 k increment of vdp for exiting 2.75 v s upply m ode increment from v dp_2.75v v dp_inc 115 170 225 mv debounce t ime for exiting 2.75 v s upply m ode t ex it _ mode1 3 4 5 m s delay t ime to recover to 2.75 v s upply m ode v dp < v dpl in bc1.2 m ode t rec_ mode1 3 4 5 s ec output driver section output voltage low v in =5 v, i gate =100 ma v ol 0.16 0.25 v output voltage high v in =5 v v oh 4.5 v rising time ( 7 ) v in =5 v, c l =3300 pf, gate=1 v ~ 4 v t r 20 35 ns falling time ( 7 ) v in =5 v, c l =3300 pf, gate=4 v~ 1 v t f 9 ns propagation delay to out high (lpc trigger) v in =5 v, gate=1 v t pd - high - lpc 44 80 ns propagation delay to out low (lpc trigger) ( 7 ) v in =5 v, gate=4 v t pd - low - lpc 30 ns gate inhibit time ( 7 ) t inhibit 1.4 s fan6291qf /fan6291qh www. onsemi.com 9 electrical characteristics (continued) v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit internal res section internal res ratio ( 7 ) v in =5~12 v k res 0.150 v/v vin dropping protection ratio with two cycle lpc width=5 s, v in =5 v to 3.5 v k vin - drop 70 90 % debounce time for disable sr when vin dropping protection t sr_off 3.8 5.5 7.2 ms lpc section linear operation range of lpc pin voltage ( 7 ) v in - off < v in 5 v v lpc 0.5 v in - 1 v lpc sink current v lpc =1 v i lpc - sink 100 na sr enabled threshold voltage @high - line v lpc - high - h 1.58 v threshold voltage on lpc rising edge @high - line ( 7 ) v lpc - high - h *0.875=v lpc - th - h v lpc - th - h 1.31 v sr enabled threshold voltage @ low - line v lpc - high - l - 5 .5 v =v lpc - th - l - 5 .5 v / 0.875 v lpc - high - l - 5 .5 v 0.8 6 v threshold voltage on lpc rising edge @ low - line ( 7 ) spec.=0.45+0.05*v in , v in =5 .5 v v lpc - th - l - 5 .5 v 0.7 25 v sr enabled threshold voltage @ low - line v lpc - high - l - 9 v =v lpc - th - l - 9 v / 0.875 v lpc - high - l - 9 v 1.06 v threshold voltage on lpc rising edge @ low - line ( 7 ) spec.=0.45+0.05*v in , v in = 9 v v lpc - th - l - 9 v 0.90 v sr enabled threshold voltage @ low - line v lpc - high - l - 12 v =v lpc - th - l - 12 v / 0.875 v lpc - high - l - 12 v 1.23 v threshold voltage on lpc rising edge @ low - line ( 7 ) spec.=0.45+0.05*v in , v in = 12 v v lpc - th - l - 12 v 1.05 v falling edge threshold voltage to trigger sr ( 7 ) v lpc - th - trig 70 mv low - to - high line threshold voltage on lpc pin v in = 5 .5 v v line - h - 5 .5 v 1.84 1.9 3 2.02 v high - to - low line threshold voltage on lpc pin v in = 5 .5 v v line - l - 5 .5 v 1.75 1.8 3 1.91 v line change threshold hysteresis v line - hys - 5 .5 v= v line - h - 5 .5 v - v line - l - 5 .5 v v line - hys - 5 .5 v 0.1 v low - to - high line threshold voltage on lpc pin v in = 9 v v line - h - 9 v 2.05 2.14 2.23 v high - to - low line threshold voltage on lpc pin v in = 9 v v line - l - 9 v 1.96 2.04 2.12 v line change threshold hysteresis v line - hys - 9v= v line - h - 9v - v line - l - 9v v line - hys - 9 v 0.1 v low - to - high line threshold voltage on lpc pin v in = 12 v v line - h - 12 v 2.23 2.32 2.41 v high - to - low line threshold voltage on lpc pin v in = 12 v v line - l - 12 v 2.14 2.22 2.30 v line change threshold hysteresis v line - hys - 12v= v line - h - 12v - v line - l - 12v v line - hys - 12 v 0.1 v higher clamp voltage v lpc - clamp - h 5.4 6.2 7.0 v lpc threshold voltage to disable sr gate switching v in =5 v. lpc=3 v v lpc - dis v in - 0. 6 v enable v lpc - dis increasing v in v en - lpc - dis 4.3 0 4.4 5 4. 60 v disable v lpc - dis decreasing v in v dis - lpc - dis 4.1 0 4.2 5 4. 40 v line change d ebounce from low - line to high - line t lpc - lh - debounce 15 23 31 ms line change d ebounce from high - line to low - line ( 7 ) t lpc - hl - debounce 15 s fan6291qf /fan6291qh www. onsemi.com 10 7. guaranteed by design. 8. guaranteed at - 5 ~ 85c. electrical characteristics (continued) v in =5 v , lpc=1.5 v, lpc width=2 s at t j = - 40~125 ? c, f lpc =100 khz, unless otherwise specified. parameter test conditions symbol min typ max unit internal timing section ratio between v lpc & v res v in =5.5 v, f lpc =50 khz, k res =0.15 ratio lpc - res 3.8 8 4.09 4.3 0 minimum lpc time to enable the sr gate @ high - line v lpc =3 v t lpc - en - h 150 2 5 0 350 ns minimum lpc time to enable the sr gate @ low - line v lpc =1 .5 v t lpc - en - l 520 620 720 ns minimum gate width ( 7 ) t min 0.35 0.5 0 0.65 s minimum gate limit on - time t gate - limit - min 0.6 1.0 1.4 s t on - sr (n+1) - t on - sr (n) < t gate - limit t gate - limit 500 ns limitation between lpc rising edge to next lpc rising edge max. period t max - period 28 40 52 s forced internal ct reset time ( 7 ) t ct - reset 10 n s reverse current mode section reverse current mode entry debounce time v in =5 v, v lpc =0 v t reverse - debounce 350 500 650 ms operating current during reverse current mode v in =5 v, v lpc =0 v i op.reverse 1.7 ma source current on cc1 pin during reverse current mode v in =5 v, v lpc =0 v i p - cc1.reverse 10 a source current on cc2 pin during reverse current mode v in =5 v, v lpc =0 v i p - cc2.reverse 10 a aux pin current during reverse current mode v in =5 v, v lpc =0 v , after t bld - max i bld.reverse 10 a data line over - votlage protection dp pin over - voltage protection excepting 2.75 v s upply m ode v dp - ovp 4.10 4.35 4.60 v dn pin over - voltage protection excepting 2.75 v s upply m ode v dn - ovp 4.10 4.35 4.60 v dp/dn pin ovp debounce time v dn > v dn - sd t dn - dp - ovp - debounce 1.5 3.0 4.5 ms fan6291qf /fan6291qh www. onsemi.com 11 typical characteristics figure 3 turn - on threshold voltage (v in - on ) vs. temperature figure 4 turn - off threshold voltage (v in - off ) vs. temperature figure 5 reference voltage at 5 v (v cvr - 5v ) vs. temperature figure 6 reference voltage at 9 v (v cvr - 9v ) vs. temperature figure 7 reference voltage at 12 v (v cvr - 12v ) vs. temperature figure 8 v in under - voltage - protection enable, 7 v (v in - uvp - l - 7v ) vs. temperature fan6291qf /fan6291qh www. onsemi.com 12 typical characteristics figure 9 v in under - voltage - protection enable, 9 v (v in - uvp - l - 9v ) vs. temperature figure 10 v in under - voltage - protection enable, 12 v (v in - uvp - l - 12v ) vs. temperature figure 11 minimum lpc t ime to e nable the sr gate @ low - line (t lpc - en - l ) vs. temperature figure 12 minimum lpc t ime to e nable the sr gate @ high - line (t lpc - en - h ) vs. temperature figure 13 ratio between v lpc & v res (ratio lpc - res ) vs. temperature figure 14 reference voltage of increment step via continuous mode of qc3.0 protocol (v cvr - step - inc ) vs. temperature fan6291qf /fan6291qh www. onsemi.com 13 typical characteristics figure 15 reference voltage of decrement step via continuous mode of qc3.0 protocol (v cvr - step - dec ) vs. temperature figure 16 source current on cc1 pin (i p - cc1 ) vs. temperature figure 17 source current on cc2 pin (i p - cc2 ) vs. temperature figure 18 gate high voltage at 5.5 v (v ngate - 5.5v ) vs. temperature figure 19 gate high voltage at 9 v (v ngate - 9v ) vs. temperature figure 20 gate high voltage at 12 v (v ngate - 12v ) vs. temperature fan6291qf /fan6291qh www. onsemi.com 14 applications information table 2. device line - up table series name output voltage and its nominal output load uvp o peration 3.6 ~ 6.0 v 6 . 2 ~9 .0 v 9. 2 ~12 .0 v fan6291qf 3.0 a 2.0 a 1.5 a pull - down sfb fan6291qh 3.0 a 3.0 a 2.0 a reduce cc fan6291q f and fan6291qh implement different operation method s when the uvp is triggered. fan6291qh reduces constant current level after triggering uvp. when a foldback level is performed on the system, resistive load is normally used. since this reduced constant current is lower than the resistive load in the uvp, the output voltage is collapsed and foldback can be ach ieved. fan629 1 qf pulls - down sfb pin after uvp is triggered. it then enters latch mode operation (refer to figure 28 and figure 29 ) . according to latch mode operation, the outpu t voltage is collapsed and fold back can be achieved. type - c control function description n - chan nel mosfet for load switch fan6291q implements type - c block to enable and disable an external load switch. internally adapted charge pump lets fan6291q control n - channel mosfet as a load switch. it helps whole system be more cost competitive compared to p - channel mosfet as a load switch. since the minimum pumped voltage is v bus +3 v, it is recommended to use n - channel mosfet supporting lower gate threshold level s . detail of load switch control fan6291q supports output current higher than 1.5 a. in order t o meet type - c specification, 330 a is applied on cc1 pin and cc2 pin. when rd (5.1 k ? ) is attached on either cc1 or cc2, l oad s witch is turned - on after 150 ms debounce time. as soon as l oad s witch is enabled, bc1.2 counter is enabled. to acknowledge detac hment, it needs 15 ms debounce time. when l oad s witch is turned - off, bleeder is also enabled at the same time. if vin voltage was boosted higher than 5 v before acknowledging detachment, vin voltage is returned to 5 v. protocols (auto - detection) 2.75 v s upply m ode some apple products charge higher current when a dedicated charging port sources specific voltage on d+ and d - lines. fan6291q supports 2.75 v on d+ and d - lines, respectively. apple products regard it as the attached charging port supports 2.4 a, and it charges with maximum 2.4 a. once fan6291q is enabled, d+ and d - supplies 2.75 v as default. ons intelligent auto - detection acknowledges bc1.2. as soon as bc1.2 gets started, fan6291q leaves 2.75 v supply mode immediately. after acknowledging qc3.0 or qc2.0, fan6291q does not return 2.75 v supply mode as long as a portable device is not detached. figure 21 sequence of auto - detection quick charge 3.0 (qc3.0) and quick charge 2.0 (qc2.0) protocol s as described i n table 3 , fan6291q supports up to 12 v (class a) through qc3.0 protocol. table 3. output mode of fan6291q according to quick charge 3.0 v dp v dn hvdcp output mode 0.6 v 0 v 5 v mode (backward compatible with qc2.0) 3.3 v 0.6 v 9 v mode (backward compatible with qc2.0) 0.6 v 0.6 v 12 v mode (backward compatible with qc2.0) 0.6 v 3.3 v continuous mode 3.3 v 3.3 v reserve (keep previous status) within continuous mode, output - voltage can be increased or decreased with 200 mv step per an increment or decrement protocol, respectively. (refer to figure 22 and figure 23 which are examples of increment and decrement). fan6291q can enter continuous mode from any of 5 v, 9 v and 12 v modes. however, it can return to 5 v mode from continuous mode. 2 . 7 5 v s u p p l y m o d e ( d p 2 . 7 5 v , d n 2 . 7 5 v ) b c 1 . 2 m o d e ( d p & d n s h o r t ) ? v d p > v d p _ i n c f o r t e x i t _ m o d e 1 o r v d p < v d p h f o r t e x i t _ m o d e 1 o r v d n < v d n h f o r t e x i t _ m o d e 1 v d p l < v d p < v d p h f o r t b c 1 . 2 v d p l > v d p f o r t r e c _ m o d e 1 v d p < v d p h f o r t d i s c o n n e c t h v d c p m o d e ( d p r d p , d n r d n ) d e t a c h p o w e r o n r e s e t a c k n o w l e d g e q c 3 . 0 o r q c 2 . 0 fan6291qf /fan6291qh www. onsemi.com 15 figure 22 example of increment timing diagram (800 mv i ncrement from 5 v ) figure 23 example of decrement timing diagram (600 mv decrement from 5.8 v) communication function description constant voltage control the internal constant voltage control block regulates adaptive output voltages. output voltage is sensed through an external resistor divider. the sensed output voltage is connected to the vref w hich is the non - inverting input terminal of the internal operational amplifier. the inverting input terminal is connected to the internal voltage reference (v cvr ) which can be adjusted according to the requested output voltage via quick charge 3.0 protocol . the amplifier and an internal switch operate as a shunt regulator. the output of the shunt regulator is connected to the external opto - coupler, and this pin is named as secondary feedback (sfb). to compensate output voltage regulation being stable, one c apacitor and one resistor are connected typically between the sfb and vref pins as shown in figure 24 . the output voltage can be derived as shown in equation ( 1 ) and the recommended ratio of the resistor divider is 5. ( 1 ) constant current control in order to support adaptive constant output current, fan6291q incorporates the constant - current control circuit internally. output current is sensed via a current - sens e resistor, r cs , which is connected between the cs pin and gnd pin. t he sensed signal is internally amplified , and this amplified voltage is connected to the non - inverting input of the internal operation amplifier. likewise the constant voltage amplifier circuit, it also p lays a role as a shunt regulator to regulate the constant output current . in order to compensate output current regulation, one capacitor and one resistor are connected between iref and sfb pins typically as the figure 24 . the c onstant output current is decided by the equation ( 2 ) . 30 m is typically used for the sense resistor. ( 2 ) since cs pin senses small amounts of voltage, the sensing resistor should be positioned as close as possible to cs pin. shown in figure 24 , an rc low pass filter can be added on the cs pin to be immunized from noise. figure 24 constant voltage and constant current circuit gr een mode operation in order to reduce power consumption at light - load condition s , fan6291q enters the green mode. when v cs which is the voltage between cs and gnd pins is smaller than v cs - green with longer duration than t green - en - debounce , fan6291q enters the green mode. typical output curr ent entering the green mode is 17 0 ma. while it operates in the green mode, some internal blocks are disabled such as s ynchronous r ectifier control block. therefore, the operating current can be reduced to 1.2 ma (typ.). it leaves green mode when v cs is larger than v cs - green with longer duration that t green - dis - debounce . d p d n 3 . 3 v 0 . 6 v 3 . 3 v 0 . 6 v b u s 5 . 8 v 5 v t g l i t c h _ c o n t _ c h a n g e 4 h i g h / l o w p u l s e s = 0 . 2 v * 4 = 0 . 8 v s t a r t o f c o m m u n i c a t i o n e n d o f c o m m u n i c a t i o n d p d n 3 . 3 v 0 . 6 v 3 . 3 v 0 . 6 v b u s 5 . 8 v 5 . 2 v 3 h i g h / l o w p u l s e s = 0 . 2 v * 3 = 0 . 6 v s t a r t o f c o m m u n i c a t i o n e n d o f c o m m u n i c a t i o n t g l i t c h _ c o n t _ c h a n g e 12 2 ? ?? ff o cvr f rr vv r ? - v b u s f b r c s r f 1 r f 2 v c v r s f b v r e f v c c r i r e f a v - c c r g n d c s c c a m p c v a m p cs ccr ccr v cc o r v a i ? ? - 1 _ fan6291qf /fan6291qh www. onsemi.com 16 cable drop compensation to regulate the output voltage constantly at the end of a cable regardless of output current, the cable drop compensation function is implemented. the weight of compensation is internally fixed. the compensated output voltage is described in equation ( 3 ) . ( 3 ) output ovp also implements cable drop compensation. ratio of cable drop compensation for output ovp is different with cable drop compensation for constant voltage regulation shown in equation ( 4 ) . ( 4 ) figure 25 cable - drop compensation block bleeder section when a p ortable d evice requests to reduce output voltage via quick charge 3.0, bus voltage should be decreased. w hen the p ortable d evice is detached, vin voltage should be returned to 5 v and bus voltage should be discharged to zero within a short time. since the dischargi ng time is very long at light - load condition, fan6291q supports the bleeding function. the bleeder function is enabled during t bld - max . the bleeding current via vin pin cannot be controlled. however, the amount of bleeding current through bld pin can be co ntrolled by the external resistor (r bld ) shown in equation ( 5 ) . ( 5 ) s i nce there can be output voltage undershoot during b leeding time if summation of output load current and bleeding current is larger than cc level, bleeding function is disabled when output current is larger than 40 0 ma (typ.). output over - voltage protection figure 26 shows the output o ver - v oltage p rotection (ovp) block , which is adaptive according to output voltage status . once the sensed output voltage via vin pin is larger than v in - ovp longer than t d - ovp , the internal ovp switch is enabled with latch mode . and the latch mode of fan6291q is re set when v in < v latch - off . when fan6291q is compatible with fan602, v s - uvp of fan602 can be triggered after releasing latch mode of fan6291q . according to protect ion mode of v s - uvp of fan602, v in - ovp of fan6291 q is operated as extended auto - restart mode or l atch mode. table 2 . o ver - voltage protection threshold level symbol v out range ovp level (typ.) v in - ovp - 5v 3.6 v ~ 5.0 v 6.0 v v in - ovp - 6v 5.2 v ~ 6.0 v 8.4 v v in - ovp - 9v 6.2 v ~ 9.0 v 10.8 v v in - ovp - 12v 9.2 v ~ 12.0 v 14.4 v figure 26 output over - voltage protection block output under - voltage protection in order to support foldback level of each output mode, the output under voltage protection (uvp) function is incorporated. the uvp function can reduce power delivery during output soft - short fault. figure 26 shows its implementation . once vin voltage is lower than v in - uvp - l longer than t d - vin - uvp , the constant current level is reduced to 220 ma (typ.). fan6291q leaves uvp when vin voltage is higher than v in - uvp - h . while the uvp is operated, the synchronous rectifier control is disabled to avoid shoot - through. some option versions enter the latch mode instead of reducing output current after triggering uvp. the uvp function is only enabled when qc2.0 protocol is accepted. for qc3.0 mode, uvp funct ion is disabled. table 3 . under - voltage protection threshold level symbol v out range u vp level (typ.) v in - uvp - l - 9v 9 v of qc2.0 5.50 v v in - uvp - h - 9v 6.00 v v in - uvp - l - 12v 12 v of qc2.0 8.00 v v in - uvp - h - 12v 8.50 v 2 2 2 1 out f f f cdc comr on compensati out i r r r v v ? ? ? ? - - 2 out ovp comr ovp in ovp i v v v ? ? ? - - c a b l e d r o p c o m p e n s a t i o n v c v r x a v c c r m o d e r f 1 r f 2 r c s c o u t i o c s g n d v r e f r c a b l e - b u s v b u s @ c a b l e e n d u s b u s b v i n m o d e o v p r c a b l e - g n d v b u s @ p c b e n d r c s c o u t v b u s o v p c o m p a r a t o r v i n - o v p s f b v i n l a t c h - o f f q d r s t internal bld max o rtype bld r r v i ? ? - _ fan6291qf /fan6291qh www. onsemi.com 17 figure 27 output under - voltage protection block d+/d - data line over - voltage protection even though severe fault is occurred between bus and ground, monitoring data line status also can protect usb fault condition indirectly because data lines (d+/d - ) may be polluted at the same time with bus line pollution. therefore, fan6291q implements data line over - voltage - protection. it can protect when the bus and d +/d - a re short - circuited with small impedance . when voltage on d+ line and/or d - lin e is higher than v d p - ovp and /or v d p - ovp longer than v dn - dp - ovp - debounce , over voltage protection is triggered . after detecting fault condition, fan6291q enters latch mode. when fan6291q releases the latch mode, fan602 enters vs - uvp. latch mode operation fan6291q implements latch mode operation to deliver fault conditions which are detected on secondary - side to primary - side. when one fault condition is triggered among c able f ault protections, o ver - v oltage p rotection and u nder - v oltage p rotection, sfb is started to be pulled - down with latch mode. t his latch mode is released when vin voltage is lower than v la tch - off which is lower than v in - off . as shown on figure 29 , after the latch mode is released , the primary - side controller leaves burst mode and starts switching again. since the v latch - off is much lower than output voltage level which triggers v s - uvp of the primary - side controller , after releasing l atch mode, the primary - side controller triggers v s - uvp . therefore, throughout implementing the latch mode operation, the primary - side controller can trigger v s - uvp , and the system can enter l atch mode. when not only v in - ovp and cable fault protection are triggered, but also vin voltage is lower than v in - off , the latch mode is enabled, either. the latch mode operation for v in - off avoids that system becomes open - loop when v in < v in - off . figure 28 conceptual latch mode block figure 29 waveform of latch mode operation reset circuit on vref and iref vref and iref pins are connected to v in through compensation circuits. when cv and cc amplifiers are not enabled, vref and iref pin voltages are also increased according to increased v in voltage (dot lines on figure 30 ). the voltages on vref and iref are higher than target threshold levels. the reset circuit on vref and iref are implemented as each pin is connected to ground through internal switches. the iref pin is additionally reset during t start - dis - cc . reset circuit pulls - down current, and these currents (ireset_vref and ireset_iref) can flow through compensation circuits. if current flowing through the opto - coupler is large enough, the primary controller enters burst mode and triggers vs - uvp - h, because of this startup may fail. rbias helps to decrease current flowing through the opto - coupler, to avoid startup failure. the rbias design depends on compensation design, typically 2~6 k? is recommended. v c c r m o d e r c s c o u t v b u s i o v i n u v p p r o t e c t i o n x a v c c r c s g n d i r e f s f b l a t c h - o f f q d r s t r c s c o 1 c o 2 v b u s v l a t c h - o f f v i n q d r s t p r i m a r y f b s f b c a b l e f a u l t s v i n - o v p v i n - u v p v i n - o f f v o u t v s f b v d d . p r i v f b v l a t c h - o f f v b u r s t v o u t @ v s - u v p i d s l a t c h m o d e f a u l t v s - u v p fan6291qf /fan6291qh www. onsemi.com 18 figure 30 reset circuit operation figure 31 reset circuit and r bias pcb layout guidelines printed circuit board (pcb) layout and design are very important for switching mode power supplies where the voltage and current change with high speed. good pcb layout minim izes electro - magnetic interference ( emi ) and prevents excessive noise from surge or electro - static discharging (esd). as shown in figure 33 c out1 and c out2 are the output capacitors; q 2 is the secondary - side sr mosfet. the following guidelines are recommended for layout designs. ? the main power flows through q2, c out1 , c out2 and r cs . this power path should be separated with signal grounds which are connected to fan6291q . in addition, it is recommended that p ower ground is directly connected to y - cap. refer to figure 32 . ? the sensed voltage via r cs is very small value. in order to avoid offset voltage or avoid inducing switching noise on the sensed voltage, r cs should be connected between ground of c out2 and power ground. and r cs sh ould be positioned as close as possible to cs pin and gnd pin. refer to figure 33 . ? to avoid switching noise i nterference to synchronous rectifier operation, r lpc - h and r lpc - l should be close to fan6291q . and power path should be apart from lpc path. figure 32 power and signal ground on the secondary - side figure 33 examples of sensing resistor connection e n a b l e r e s e t c i r c u i t v i n - o n v i n v r e f i r e f t s t a r t - d i s - c c t i m e t i m e t i m e v c v r - 5 v v i r e f @ c c w i t h o u t r e s e t c i r c u i t w i t h o u t r e s e t c i r c u i t ? - v b u s f b r c s r f 1 r f 2 v c v r s f b v r e f v c c r i r e f a v - c c r g n d c s r b i a s r e s e t i r e s e t _ i r e f i r e s e t _ v r e f p o w e r g n d s i g n a l g n d s i g n a l g n d s r m o s f e t r s e n s e c o u t b l d l g a t e v i n v r e f g a t e l p c d p d n g n d c s d n d p i r e f c c 1 c c 1 s f b c c 2 c c 2 l o a d s w i t c h v b u s f a n 6 2 9 1 c o u t 2 v o c o u t 1 c o u t 2 v o c o u t 1 b a d c o n n e c t i o n ; r c s s h o u l d n o t b e c o n n e c t e d b e f o r e c o u t 2 w r o n g c o n n e c t i o n ; r c s m u s t n o t c o n n e c t e d b e t w e e n c o u t 1 a n d c o u t 2 r s e n s e c o u t 2 v o c o u t 1 g o o d c o n n e c t i o n c o u t 2 v o c o u t 1 b a d c o n n e c t i o n ; c s & g n d s h o u l d b e c l o s e d t o r c s g n d c s g n d c s g n d c s g n d c s r p a t t e r n r p a t t e r n r s e n s e r s e n s e r s e n s e fan6291qf /fan6291qh www. onsemi.com 19 ordering information part number operating temperature range package packing method fan6291q fmtcx - 4 0 ? c to + 1 2 5 ? c 1 4 - lead, ts sop jedec mo - 153, 4.4 mm wide tape & reel fan6291q hmtcx - 4 0 ? c to + 1 2 5 ? c 1 4 - lead, ts sop jedec mo - 153, 4.4 mm wide tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d front view top view ? all lead tips notes: a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters. c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions d. dimensioning and tolerances per ansi y14.5m, 2009. e. landpattern standard: sop65p640x110-14m. f. drawing file name: mkt-mtc14rev7. 0.43typ 0.2 c b a 8 1 7 14 a b ? 3.2 6.4 pin#1 ident 1.2 max 0.1 c all lead tips c 0.65 0.30 0.19 0.13 a b c ? 0.90 +0.15 -0.10 0.20 0.09 see detail a ? 7 2 3 % 2 7 7 2 0 gage plane 0.25 seating plane 0.09 min 0.09 min ? 1.00 detail a ? ? recommended land pattern 6.10 0.65 1.65 0.45 www. onsemi.com 1 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 www.onsemi.com literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ? semiconductor components industries, llc |
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